1. Field of the Invention
The present invention relates to a semiconductor module and a method for mounting the same.
In the invention, a term ‘a substantially fixed length’ includes ‘a fixed length.’
2. Description of the Related Art
In recent years, as miniaturization of mobile electronic equipment and mobile electronic apparatuses such as mobile telephones and mobile information terminals is requested, it is promoted to miniaturize semiconductor modules and increase the densities thereof. In order to promote miniaturization of the semiconductor modules in this way, a stacked-type semiconductor module structure such that a plurality of semiconductor devices are stacked is proposed. It is possible to realize the stacked-type semiconductor module by mounting the semiconductor devices on a flexible board and folding the board.
FIG. 6 is a cross sectional view of a mounting structure of a semiconductor module 100 of a first related art taken on a virtual plane including a board in a thickness direction thereof. FIG. 7 is a cross sectional view of the semiconductor module 100 in a developed state. FIG. 8 is a circuit view schematically showing a transmission circuit of the semiconductor module 100. The semiconductor module 100 of the first related art comprises a flexible wiring board 105 and four semiconductor devices 101.
On one surface portion of the wiring board 105, the four semiconductor devices 101 are mounted as shown in FIG. 7. Moreover, on the wiring board 105, an external connecting terminal 107 and printed wiring 106 are formed. The external connecting terminal 107 includes an external input terminal 107a to which signals are inputted and an external output terminal 107b that outputs signals. The printed wiring 106 electrically connects the external input terminal 107a and the external output terminal 107b to the respective semiconductor devices 101. Consequently, it is possible to transmit signals inputted to the external input terminal 107a to the respective semiconductor devices 101. Moreover, it is possible to transmit signals from the respective semiconductor devices 101 to the external output terminal via the printed wiring 106.
Further, since the wiring board 105 has flexibility, it is possible to fold the wiring board 105 so that the respective semiconductor devices 101 are stacked. By thus folding the wiring board 105, it is possible to form the semiconductor module 100. The semiconductor module 100 formed in this way has a mounting area approximately one quarter of a mounting area of a semiconductor module such that the four semiconductor devices 101 are mounted in the longitudinal direction without folding the wiring board 105 (refer to Japanese Unexamined Patent Publication JP-A 6-69279 (1994) (FIG. 1, pages 2 to 3) and United States Patent Publication U.S. Pat. No. 6,121,676 (FIG. 5, page 4), for example).
FIG. 9 is a plan view showing a stacked-type mounting body 110 of a second related art in a developed state. FIG. 10 is a simplified circuit view showing a transmission circuit of the stacked-type mounting body 110. The stacked-type mounting body 110 comprises a base element 111, four film carrier elements 112, and bending portions 113. The base element 111 and the four film carrier elements 112 are formed by substantially square insulating boards, and conducting lines 114 are disposed inside. Moreover, semiconductor devices can be mounted on the conducting lines 114 of the base element 111 and the four film carrier elements 112. The respective film carrier elements 112 of the base element 111 and the base element 111 are mechanically connected to each other at side face portions via the bending portions 113. Consequently, the stacked-type mounting body 110 is formed into a cross shape such that the base element 111 is placed in the center.
Further, the bending portion 113 are formed by flexible insulating boards. Consequently, it is possible to fold the bending portions 113 so that the four film carrier elements 112 are stacked on the base element 111, and form the stacked-type mounting body 110 such that the four film carrier elements 112 are stacked on the base element 111. Moreover, the conducting lines 114 are disposed inside the bending portions 113.
The conducting lines 114 of the respective film carrier elements 112 and the conducting lines 114 of the base element 111 are electrically connected via the conducting lines 114 of the bending portions 113. Consequently, it is possible to transmit signals between the respective film carrier elements 112 and the base element 111. Moreover, the conducting lines 114 are formed so that wiring lengths from the base element 111 to the respective film carrier elements 112 become a substantially fixed length.
In the stacked-type mounting body 110 formed in this way, the wiring lengths from the base element 111 to the respective film carrier elements 112 are a substantially fixed length. Therefore, in the case of transmitting the same signals from the base element 111 to the respective film carrier elements 112, the sum of a transmission time for transmitting signals from the base element 111 to each of the film carrier elements 112 and a transmission time for transmitting signals from each of the film carrier elements 112 to the base element 111 becomes a substantially fixed time. Consequently, it is possible to avoid a reading error that results from a difference in transmission times when the base element 111 reads signals transmitted from the respective film carrier elements 112 to the base element 111 (refer to Japanese Unexamined Patent Publication JP-A 11-40618 (1999) (FIG. 2, pages 3 to 4), for example).
FIG. 11 is a simplified circuit view showing a bus system 120 of a third related art. The bus system 120 comprises a master device 121, three slave devices 122, a data bus 123, a clock bus 124, and a clock 125.
To the master device 121 and the three slave devices 122 (‘the master device 121 and the three slave devices 122’ maybe referred to as ‘the devices 129’ hereinafter) the data bus 123 and the clock bus 124 are electrically connected. The devices 129 are capable of subjecting inputted signals to operation processing and outputting the signals.
The data bus 123 is capable of making signals inputted from one end portion thereof. To another end portion of the data bus 123, the master device 121 is electrically connected. Moreover, to a middle portion of the data bus 123, the slave devices 122 are electrically connected. When signals are inputted, the data bus 123 can transmit the signals to the respective devices 129. Moreover, the data bus 123 is capable of transmitting signals outputted from the respective devices 129 to the one end portion.
The clock bus 124 has first and second segments 126, 127 and a middle and vicinity portion 128. One end of the clock bus 124 is electrically connected to the clock 125. The clock bus 124 is folded at the middle and vicinity portion 128 of the whole length thereof. Of the clock bus 124, a side from the middle and vicinity portion 128 to a portion connected to the clock 125 is referred to as the first segment 126, and the rest is referred to as the second segment. The first segment 126 and the second segment 127 are electrically connected to the respective devices 129.
The clock 125 has a function of generating clock signals and transmitting the clock signals to the respective devices 129 via the clock bus 124.
The clock signals are inputted to the respective devices 129 via the clock bus 124. When the clock signals are inputted from the first segment 126 to the respective devices 129, the respective devices 129 receive signals inputted from the data bus 123. Moreover, when the clock signals are inputted from the second segment 127 to the respective devices 129, operated signals are outputted from the respective devices 129 to the data bus 123. Consequently, signals inputted to the respective devices 129 are not outputted until the clock signals are received from the second segment 127 after the devices 129 receive the clock signals from the first segment 126 and make the signals inputted. Therefore, in the respective devices 129, a time between input and output, that is, a transmission standby time is generated.
In the bus system 120, the data bus 123 and the clock bus 124 are formed so that the sum of a transmission standby time in each of the devices 129, a time for transmitting signals inputted to the data bus 123 to each of the devices 129, and a time for transmitting from each of the devices 129 to the one end of the data bus 123 becomes a substantially fixed time. Consequently, whichever one of the devices 129 signals inputted to the data bus 123 are transmitted through to the one end of the data bus 123, a transmission time becomes a substantially fixed time. The transmission time is synonymous with a time between input of signals to a device such as the data bus 123 and output from the device. Therefore, it is possible to minimize clock data skews of the respective devices 129 of the bus system 120 (refer to Japanese Published Unexamined Patent Application based on International Application JP-A 7-506920 (1995)(FIG. 3, pages 4 to 5)).
The semiconductor module 100 of the first related art is formed by folding the wiring board 105 and stacking the four semiconductor devices 101. On this occasion, regarding the printed wiring 106, the line lengths of the printed wiring 106 electrically connected to the external connecting terminal 107 vary depending on the respective semiconductor devices 101. Depending on whichever semiconductor device signals inputted from the external input terminal 107a are transmitted through to the external output terminal 107b, a transmission time is different. Consequently, a difference in times for transmitting signals outputted from the respective semiconductor devices 101 to the external output terminal 107b, that is, a transmission delay time is generated.
There is a case where the circuit board with the semiconductor module 100 mounted cannot read signals outputted from the external output terminal 107b, that is, a reading error occurs because of the transmission delay time. The reading error occurs when the transmission delay time exceeds a quarter of one cycle of inputted signals. Therefore, in order that the circuit board does not cause the reading error, the semiconductor module 100 needs to be formed so that the transmission delay time becomes a quarter or less of one cycle of inputted signals, and therefore, it is inconvenient.
Further, when the transmission delay time exceeds a quarter of one cycle of inputted signals, it is necessary to change timing for reading signals on the basis of the transmission delay time, so that there is a problem such that circuit designing is complicated.
In the stacked-type mounting body 110 of the second related art, the sum of a time for transmitting signals from the base element 111 to each of the film carrier elements 112 and a transmission time for transmitting signals from each of the film carrier elements 112 to the base element 111 becomes a substantially fixed time. Consequently, it is possible to inhibit occurrence of the reading error as in the semiconductor module 100 of the first related art, but it is necessary to input signals to the base element 111 once in the case of transmitting signals to the respective film carrier elements 112, and therefore, it is inconvenient. Moreover, in the case of mounting the base element 111 on the circuit board, it is easy to match the impedances of an output terminal, which is not shown in the drawings, of the base terminal 111 and the circuit board at the time of inputting signals, but it is difficult at the time of outputting. Consequently, in the case of transmitting high-frequency signals in the stacked-type mounting body 110, reflection of signals occurs on the circuit board, and signals are disturbed.
The bus system 120 of the third related art can eliminate a difference in transmission times of the respective devices 129 by clock signals transmitted from the clock 125. In this case, in the bus system 120, the transmission standby time is set so that transmission times of the respective devices 129 become substantially the same as the largest transmission time of the transmission times of the respective devices 129. In other words, the transmission times of the devices 129 are substantially the same as the transmission time of the master device 121 in specific. Therefore, the transmission times of the respective devices 129 become large, so that it is inconvenient. Moreover, it is necessary to dispose the data bus 123, the clock bus 124 and the clock 125, and therefore, the conducting circuit becomes complicated.